The present invention relates to a digital to analog converter for converting a digital signal to an analog signal. More particularly, the invention relates to a digital to analog converter suitable for obtaining high resolution, and a frequency synthesizer which uses the converter.
An example of a digital to analog converter which converts a digital signal to an analog signal is known as a digital to analog converter of a current cell matrix type. Such a converter uses current cells arranged in a matrix as disclosed in Japanese Patent Laid-Open No. 153832/1981. FIG. 13 is a block diagram showing the structure of a conventional digital to analog converter of a current cell matrix type.
The digital to analog converter of a current cell matrix type illustrated in FIG. 13 converts 6-bit digital signals to analog signals. The converter comprises a current cell array 401 made up of current cells 402 of an 8.times.8 matrix; and a first row decoder 403, a second row decoder 411, and a column decoder 406 which are used for selecting some of the current cells 402 in the current cell array 401.
The higher three bits of an input signal of six bits are supplied to the first row decoder 403 through signal lines 64 to 66. The output of the first row decoder 403 is supplied to the second row decoder 411 through signal lines 421 to 428. On the other hand, the lower three bits of the input signal of the six bits are supplied to the column decoder 406 through signal lines 61 to 63. The first row decoder 403 decodes the higher three bits of the input signal to generate first row selection signals RA0 to RA7, which are supplied to the current cell array 401 through signal lines 421 to 428, respectively.
The second row decoder 411 receives the output signals RA0 to RA7 from the first row decoder 401 to generate second row selection signals RR0 to RR7, which are supplied to the current cell array 401 through signal lines 431 to 438, respectively. The column decoder 406 decodes the lower three bits of the input signal to generate column selection signals CR0 to CR7, which are supplied to the current cell array 401 through signal lines 441 to 448, respectively.
In the current cell array 401, the common first row selection signals or the common second row selection signals are supplied to the current cells 402 belonging to the same column. Also, the common column selection signals are supplied to the current cells 402 belonging to the same column. The current cell 402 comprises, a switching circuit opened or closed in response to the first and second row selection signals and the column selection signals, and a current source. The output current of this current cell 402 can be taken out through a signal line 70 and the output signal lines 71 to 78 connected commonly to the current cells belonging to the same column.
Hereinafter, the description will be made of the operation of a digital to analog converter of a cell matrix type having such a structure by exemplifying a case where the digitally inputted signal represents "011111". When a 6-bit digital signal is inputted, the first row decoder 403 receives the higher three bits and activates one row selection signal RA3 of the first row selection signals RA0 to RA7 in accordance with the number "011" represented by the three bits. Also, the second row decoder 411 receives the first row selection signals RA0 to RA7, and activate the row selection signals RR0 to RR2 identical to the number "011" represented by the higher three bits of the input signal of six bits among the second row selection signals RR0 to RR7. Then column decoder 406 receives the lower three bits of the input signal of six bits, and activates the column selection signals CR0 to CR6 identical to the number "111" represented by the lower three bits of the input signal of six bits among the column selection signals CR0 to CR7.
The switching circuit of each current cell 402 receives these three kinds of selected signals. When the first row selection signal and column selection signal are both in the activated state or when the second row selection signal is in the activated, the switching circuit is closed and thereby, the current cell is made in an output state. In this example, the total of 31 current cells are in the output state: these are seven current cells belonging to the columns to which are connected the signal lines 441 to 447 in the row where the signal line 424 is connected, and 24 current cells belonging to the rows to which the signal lines 431 to 433 are connected.
It is conceivable to use a technique which uses a temporal interpolation in order to obtain a resolution higher than that of a digital to analog converter of this kind. For example, a signal is generated which repeats at a high speed a number "011111", and a number "100000" which is greater than the former number by 1. Then this signal is converted from digital to analog. The output of the digital to analog converter is smoothed by use of a filter having low-pass properties. In this way, it is possible to obtain the intermediate output value between the output value "011111" and the output value "100000", hence equivalently obtaining a resolution of seven bit by use of a six-bit digital to analog converter.
A technique which uses a delta-sigma modulation is shown in FIG. 14 as an example of obtaining a signal sequence for such a temporal interpolation. FIG. 14 is a block diagram showing an example of the structure of a digital to analog converter which uses digital-sigma modulation. In FIG. 14, a digital to analog converter having a 10-bit resolution uses a four-bit delta-sigma modulator (in FIG. 14, named a .DELTA..SIGMA. modulator) 100, a delay device 200, an adder 300, a six-bit digital to analog converter of current cell matrix type 400, and a low-pass filter 500. Hereunder, the description will be made of the operation of this digital to analog converter when a 10-bit signal 1 "0111110001" is inputted into the converter. of the input signal 1, the lower four-bit signal 3 representing "0001" is inputted into the delta-sigma modulator 100, and converted into one-bit signal 5. This one-bit signal 5 is a signal sequence comprising "0" and "1". Since this signal expresses one LSB in the case of a 4-bit resolution, "0" and "1" appear at a ratio of 15:1 in synchronism with a high sampling frequency of the delta-sigma modulator 100.
On the other hand, a six-bit signal 2 representing "011111" of the input signal 1 is delayed by the delay device 200 having stages the number of which is identical to the delay between the input and output of the delta-sigma modulator 100. After that, this signal is added by the adder 300 to the one-bit signal 5 from the delta-sigma modulator 100 However, if the six-bit signal 2 represents "111111", it is necessary to prohibit the addition in order to avoid overflow resulting from a carry. As the result of the addition by the adder 300, these signals become a six-bit signal sequence 6 in which the digital values "011111" and "100000" appear at a ratio of 15:1. This signal sequence 6 is converted into analog values by the six-bit digital-analog converter 400 of a current cell matrix type shown in FIG. 13 in detail. The output current 7 is converted into voltage by the lowpass filter 500, and the components of high frequency are removed, thus obtaining an analog output signal 8 having a resolution of 10 bits.
Now, in conjunction with FIG. 15 and FIG. 16, the description will be made of the operation of the digital to analog converter 400 of a current cell matrix type at that time. FIG. 15 and FIG. 16 are explanatory views illustrating an operation example of the digital to analog converter of a current cell matrix type shown in FIG. 13. The example shown in FIG. 15 illustrates schematically the output signals RA0 to RA7 and RR0 to RR7 of the first and second row decoders 403 and 411, the output signals CR0 to CR7 of the column decoder 406, and the states of the current cells of the current cell array 401 in FIG. 13 when the input digital signal represents "011111".
In FIG. 15, a reference numeral 174 denotes the status of the first row selection signal. It shows that only the output signal RA3 is active among the first row selection signals when the higher three bits of "011" are decoded by the first row decoder 403 shown in FIG. 13. A reference numeral 173 denotes the status of the second row selection signals. It shows that the RR0 to RR2 of the second row selection signals are active when the first row selection signals are decoded by the second row decoder 411 in FIG. 13. A reference numeral 175 denotes the status of the column selection signals. It shows that only the CR0 to CR6 are active among the column selection signals when the lower three bits of "111" are decoded by the column decoder 406 shown in FIG. 13.
In the current cell array 401, the current cells 171 are in the output state when the first row selection signals and column selection signals are activated, and the current cells 172 are in the output state when the second row selection signals are activated. Therefore, when the input digital signal is "011111", 31 current cells are in the output state.
The example shown in FIG. 16 schematically illustrates the output signals (RA0 to RA7, RR0 to RR7, and CR0 to CR7) of the decoders (first and second row decoders 403 and 411, and column decoder 406), and the states of the current cells 402 in FIG. 13 when the input digital signal represents "100000".
In FIG. 16, a reference numeral 177 denotes the status of the first row selection signal. It shows that only RA4 is active among the first row selection signals when the higher three bits of "100" are decoded by the first row decoder 403 in FIG. 13. Also, a reference numeral 178 denotes the status of the second row selection signals. It shows that the RR0 to RR3 of the second row selection signals are active when the first row selection signals are decoded by the second row decoder 411 in FIG. 13. Also, a reference numeral 179 denotes the status of the column selection signals. It shows that all the column selection signals are inactive when the lower three bits of "000" are decoded by the column decoder 406 in FIG. 13.
Of the current cell array 401, the current cells 176 are the current cells in the output state when the column selection signals are activated. Therefore, 32 current cells are in the output state when the input digital signal represents "100000".
The two kinds of input digital signals shown in FIG. 15 and FIG. 16 are repeated and the analog outputs of the input digital signals are smoothed. Thus it is possible to obtain a resolution which is higher than that which the digital to analog converter inherently has.
The digital to analog converter which utilizes the delta-sigma modulator is used for audio equipment, communication equipment, and the like. However, when such a conventional digital to analog converter of a current cell matrix type is used, glitches are generated because the row selection signals take wrong statues temporarily when the row selecting the input digital signal is changed and when temporary delay exists between the response of the first row decoder 403 and second row decoder 411 in FIG. 13. In the digital to analog converter which uses the delta-sigma modulator 100 as shown in FIG. 14, the row decoder operates along with the change of the output signals of the delta-sigma modulator 100 if the input digital signal of the digital to analog converter 400 of a current cell matrix type are a signal sequence in which the signal oscillate between "011111" and "100000" at a high speed. As a result, there arises a problem that a large number of glitches are generated as shown in FIG. 17.
FIG. 17 is a timing chart showing the timing status of the digital to analog converter of a current cell matrix type in FIG. 14. FIG. 17 illustrates the state in which a glitch is generated when the response of the second row decoder 411 shown in FIG. 13 is delayed by a period dt.
At the time t1, first, the activated states of the RA3 of the first row selection signals, and the column selection signals CR0 to CR6 are changed to the inactive states. Thus the selected state of the seven current cells 402 belonging to the current cells 171 in FIG. 15 is changed to the non-selected state. As a result, the output current out is decreased by a portion of 7LSBs. Next, at the time t2, the inactive state of the RR3 of the second row selection signals is changed to the activated state. Thus the non-selective state of the eight current cells controlled by the RR3 is changed to the active state. As a result, the output current Iout is increased by a portion of eight LSBs. At this time, the output current Iout is increased by one LSB from the initial state (at the time t1). However, a temporary erroneous operation during the period from t1 to t2 causes a glitch.
Therefore, a digital to analog converter of a current cell matrix type which uses a conventional delta-sigma modulator to enhance the resolution, suffers from the disadvantage that the signals for selecting current cells are generated along with the change in the output signals of the delta-sigma modulator, and if the operating time of each circuit which generates the signal for selecting current switch cells differs, a large number of glitches are generated.